A time-delay digital tanlock loop

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A time-delay digital tanlock loop

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dc.contributor.author Hussain, Z.M
dc.contributor.author Boashash, B
dc.contributor.author Hassan-Ali, M
dc.contributor.author Al-Araji, S.R.
dc.date.accessioned 2011-10-18T19:42:55Z
dc.date.available 2011-10-18T19:42:55Z
dc.date.issued 2001-08
dc.identifier.citation IEEE Transactions on Signal Processing, Issue Date : Aug 2001 Volume : 49 , Issue:8 On page(s): 1808 - 1815 en_US
dc.identifier.issn 1053-587X
dc.identifier.uri http://hdl.handle.net/10576/10763
dc.description This paper presents a nonuniform-sampling time-delay digital tanlock loop (TDTL) where the conventional constant 90 degree phase shifter is replaced by a time-delay unit. This is to avoid many of the practical problems associated with the implementation of the digital Hilbert transformer, (Additional details can be found in the comprehensive book on Time-Frequency Signal Analysis and Processing (see http://www.elsevier.com/locate/isbn/0080443354). In addition, the most recent upgrade of the original software package that calculates Time-Frequency Distributions and Instantaneous Frequency estimators can be downloaded from the web site: www.time-frequency.net. This was the first software developed in the field, and it was first released publicly in 1987 at the 1st ISSPA conference held in Brisbane, Australia, and then continuously updated). en_US
dc.description.abstract We propose a nonuniform sampling digital tanlock loop (DTL) that utilizes a constant time-delay unit instead of the constant 90° phase shifter The new structure reduces the complexity of implementation and avoids many of the practical problems associated with the digital Hilbert transformer like the approximations and frequency limitations. The time-delay digital tanlock loop(TDTL) preserves the most important features of the conventional DTL (CDTL), such as reduced sensitivity to the variation of the signal power. It also introduces improvement over the first-order CDTL under suitable choice of the circuit parameters. The first- and second-order loops are analyzed for locking conditions and steady-state phase error. en_US
dc.description.sponsorship IEEE Signal Processing Society en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject DC-free conditions en_US
dc.subject DPLL en_US
dc.subject circuit parameters en_US
dc.subject constant time-delay unit en_US
dc.subject convergence behavior en_US
dc.subject digital clock en_US
dc.subject digital controlled oscillator en_US
dc.subject digital loop filter en_US
dc.subject digital phase-locked loops en_US
dc.subject first-order CDTL en_US
dc.subject first-order loop en_US
dc.subject implementation complexity reduction en_US
dc.subject locking conditions en_US
dc.subject noise-free conditions en_US
dc.subject nonuniform sampling digital tanlock loop en_US
dc.subject performance analysis en_US
dc.subject phase error detector en_US
dc.subject reduced sensitivity en_US
dc.subject samplers en_US
dc.subject second-order loop en_US
dc.subject signal power variation en_US
dc.subject steady-state phase error en_US
dc.subject time-delay digital tanlockloop en_US
dc.subject time-delay unit en_US
dc.subject Hilbert Transform en_US
dc.subject 90 degree phase shifter en_US
dc.title A time-delay digital tanlock loop en_US
dc.type Article en_US

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