Show simple item record

AuthorZhai, Xiaojun
AuthorJaber, Fadi
AuthorBensaali, Faycal
AuthorMishra, Arti
Available date2022-12-29T07:34:47Z
Publication Date2015
Publication NameInternational Journal of Simulation: Systems, Science and Technology
ResourceScopus
URIhttp://hdl.handle.net/10576/37862
AbstractThis paper describes an image processing algorithm and its efficient architecture. The proposed architecture is used to process images of microelectrode arrays (MEAs) and micro-wells captured by a microscope camera in a dielectrophoresis (DEP)-based system which consists as well of digital switches for turning the DEP force 'on' or 'off'. The images are processed in order to determine if a neuron has entered any of the micro-wells in which case the corresponding switch turns 'off' the DEP force. This process must be in real-time to avoid more than one cell to be loaded in a micro-well. The proposed architecture has been successfully implemented and tested on a Zynq SoC. Results achieved have shown that the system can process one image in 9 ms which meets the minimum real-time requirements of this DEP system. 2015, UK Simulation Society. All rights reserved.
Languageen
PublisherUK Simulation Society
SubjectDielectrophoresis
FPGA
Microelectrode arrays
Zynq SoC
TitleHardware acceleration of a dielectrophoresis system for achieving a single-neuron-per-electrode arrangement in microelectrode arrays
TypeArticle
Pagination4.1-4.7
Issue Number3
Volume Number16


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record