المؤلف | Mohanty B.K. |
المؤلف | Al-Maadeed, Somaya |
المؤلف | Amira A. |
تاريخ الإتاحة | 2022-05-19T10:23:15Z |
تاريخ النشر | 2013 |
اسم المنشور | 2013 8th IEEE Design and Test Symposium, IDT 2013 |
المصدر | Scopus |
المعرّف | http://dx.doi.org/10.1109/IDT.2013.6727130 |
معرّف المصادر الموحد | http://hdl.handle.net/10576/31158 |
الملخص | In this paper, we present an efficient poly-phase decomposition scheme for implementation of 2-D non-separable filter bank. Poly-phase decomposition scheme offers multiplexing of filter bank computations or/and reduce the data clocking without affecting the overall throughput rate. Both these features can be used conveniently depending on resources availability or processor-technology. Time-multiplexing could be the choice for resource-constrained applications. Slower clocking rate could be chosen if processor-technology is the constraint. In that case, the design could be realized with cheaper and slower processor-technology. Time-multiplexed design needs proper data scheduling to perform filter bank computation interleavingly without data overlapping. Keeping this in mind, we have derived a systolic architecture for hardware realization of time-multiplexed filter bank where we have used novel data buffering scheme for the filter coefficients of the filter bank. Comparison result show that, the proposed structure involves almost J times less hardware resource than the non poly-phase filter bank structure and it provides the same throughput rate as the other, where J is the filter bank size. The hardware saving is significant for large size filter banks like Gabor. The proposed structure could be a good candidate for efficient hardware implementation of non-separable filter bank used in various image processing applications such as biometrics systems. |
اللغة | en |
الناشر | IEEE |
العنوان | Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank |
النوع | Conference |
dc.accessType
| Abstract Only |