FPGA-BASED ENERGY-EFFICIENT HIGH-SPEED LDPC CHANNEL CODING SCHEME FOR CUBESAT

Abstract

With the rapidly increasing demand on reliable high-speed connectivity resulting from advancements in many technologies, constellations of CubeSats present a promising opportunity to meet these demands. However, establishing high-speed connectivity using CubeSats requires pioneering solutions to overcome the difficulties associated with low-power high-speed transceivers. Demodulation and channel decoding are two of the most computationally extensive tasks of any transceiver, typically requiring high hardware-resource utilization. In this thesis, a comprehensive literature review is conducted on FPGA-based CubeSat baseband transceivers and a highly resource-efficient channel coding scheme is developed based on Low Density Parity Check (LDPC) coding. Novel low-complexity high-throughput encoding and decoding algorithms as well as their corresponding hardware architectures are developed. Detailed evaluation of the system's performance, computational complexity, and bit error rate (BER) are presented. Furthermore, extensive simulation and implementation results demonstrating the system's performance are presented. The proposed LDPC scheme achieves the same BER performance of other LDPC algorithms at lower complexity and is only outperformed by significantly more complex algorithms. Moreover, the implemented system demonstrated a throughput of 960 Mbps at a total power consumption of 2.5 W, greatly outperforming existing CubeSat systems.