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AuthorMohamed Ali, Jagabar Sathik
AuthorSiddique, Marif Daula
AuthorMekhilef, Saad
AuthorYang, Yongheng
AuthorSiwakoti, Yam
AuthorBlaabjerg, Frede
Available date2023-12-07T07:32:04Z
Publication Date2021
Publication NameInternational Journal of Circuit Theory and Applications
ResourceScopus
ISSN989886
URIhttp://dx.doi.org/10.1002/cta.3004
URIhttp://hdl.handle.net/10576/50253
AbstractThis paper proposes a new switched-capacitor nine-level (9L) inverter with reduced switch count. In the proposed topology, floating capacitor (FC) is employed as a voltage booster, and it does not need any additional sensors to maintain the voltage across the FC. Due to additional FC, the number of dc sources and voltage stress on switches is reduced. Moreover, the proposed topology can be cascaded to achieve more voltage levels. Various parameters are considered in the comparison of the proposed topology with other recent switched-capacitor topologies. Simulation and experimental results demonstrate the performance with different load and modulation index variations.
SponsorThe authors would like to thank the Ministry of Higher Education, Malaysia under the Long Term Research Grant Scheme (LRGS): LRGS/1/2019/UKM/01/6/3.
Languageen
PublisherJohn Wiley and Sons Ltd
Subjectboost inverter topology
multilevel inverter
nine levels
reduced switch count
switched-capacitor unit
TitleExperimental validation of nine-level switched-capacitor inverter topology with high voltage gain
TypeArticle
Pagination2479-2493
Issue Number8
Volume Number49
dc.accessType Abstract Only


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