Show simple item record

AuthorRebaiaia, M.L.
AuthorJaam, J.M.
AuthorHasnah, A.M.
Available date2024-03-20T01:55:09Z
Publication Date2003
Publication NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
ResourceScopus
URIhttp://dx.doi.org/10.1109/ICECS.2003.1301924
URIhttp://hdl.handle.net/10576/53283
AbstractIn this paper, we propose an efficient Model Checker for the Propositional Temporal Logic denoted by PTL. This logic is hown to be well suited to verify electronic circuits and reactive systems. A typical verification problem consists of establishing formally a relatiombip between the specification of a software/hardware system and its implementation. In the sequel we show how a bardware designer should proceed to specify his design and prove its correctness using a PTL module under Maude System. A series of experiments have been conducted successfully on a well-known benchmark to prove the effectiveness of mixing temporal logic and rewriting logic techniques.
Languageen
PublisherIEEE
SubjectComputer science
Logic circuits
Computer crashes
Boolean functions
Equations
Electronic circuits
Computer bugs
Modems
Humans
Rockets
TitleAn efficient model checker based on theaxiomatization of Propositional Temporal Logic in rewriting logic
TypeConference Paper
Pagination866-869
Volume Number2
dc.accessType Abstract Only


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record