An improved asymmetrical multilevel inverter topology with reduced semiconductor device count

Abstract

Background: Multilevel Inverters have become a viable alternative to two-level inverters because of their superior power quality, however, the increase in number of switches with their corresponding voltage stress, and dc voltage sources are the major factors for higher number of levels. Aim: This paper proposes a modified and improved asymmetrical multilevel inverter with 15 output voltage levels. Materials and Methods: The distinguishing feature of the proposed topology is the reduced number of switches as compared to recently introduced topologies having the same number of levels. As the number of devices has a direct relation to the cost of the inverter, therefore, reducing the devices will decrease the cost and makes the system more reliable for use in potential applications. The three different extensions of the proposed circuit is also discussed in the paper. Nearest level control technique is used as a modulation strategy to control the output voltage of the proposed topology. Results and Discussion: The proposed Multilevel Inverter (MLI) has been simulated in MATLAB/SIMULINK environment. The THD analysis is also shown in the paper. Experimental results have been presented and discussed to validate the obtained simulation results. Power Loss analysis of the converter is also provided. It is done with the help of PLECS software. Conclusion: The presented topology have lesser value of total standing voltage (TSV) and at the same time, there is no requirement of an H-bridge in the structure to achieve polarity reversal for the desired levels.