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المؤلفRebaiaia, M.L.
المؤلفJaam, J.M.
المؤلفHasnah, A.M.
تاريخ الإتاحة2024-03-20T01:55:09Z
تاريخ النشر2003
اسم المنشورProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
المصدرScopus
معرّف المصادر الموحدhttp://dx.doi.org/10.1109/ICECS.2003.1301761
معرّف المصادر الموحدhttp://hdl.handle.net/10576/53282
الملخصFormal verification is the task of proving that a property holds for a model of a design. This paper examines the idea of a Neural Network-based algorithm used to find the set of states that makes a specification valid. The paper addresses a singular approach for those doing theoretical research for the verification of soft programs, and, for hardware designers. The approach of the application of the Artificial Neural Network is not new, but it becomes interesting if one can improve the truth- building efficiency by using some known artifices. Topics described include Integer Linear Programming, Propositional Logic, Model Checking, Satisfiability problems (SAT) and Artificial Neural Networks (ANN).
اللغةen
الناشرIEEE
الموضوعNeural networks
Software algorithms
Neural network hardware
Circuits
Logic testing
Algebra
Logic programming
Computer science
Artificial neural networks
Formal verification
العنوانA neural network algorithm for hardware-software verification
النوعConference Paper
الصفحات1332-1335
رقم المجلد3
dc.accessType Abstract Only


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