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AuthorRebaiaia, M.L.
AuthorJaam, J.M.
AuthorHasnah, A.M.
Available date2024-03-20T01:55:09Z
Publication Date2003
Publication NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
ResourceScopus
URIhttp://dx.doi.org/10.1109/ICECS.2003.1301761
URIhttp://hdl.handle.net/10576/53282
AbstractFormal verification is the task of proving that a property holds for a model of a design. This paper examines the idea of a Neural Network-based algorithm used to find the set of states that makes a specification valid. The paper addresses a singular approach for those doing theoretical research for the verification of soft programs, and, for hardware designers. The approach of the application of the Artificial Neural Network is not new, but it becomes interesting if one can improve the truth- building efficiency by using some known artifices. Topics described include Integer Linear Programming, Propositional Logic, Model Checking, Satisfiability problems (SAT) and Artificial Neural Networks (ANN).
Languageen
PublisherIEEE
SubjectNeural networks
Software algorithms
Neural network hardware
Circuits
Logic testing
Algebra
Logic programming
Computer science
Artificial neural networks
Formal verification
TitleA neural network algorithm for hardware-software verification
TypeConference Paper
Pagination1332-1335
Volume Number3
dc.accessType Abstract Only


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