Single-phase hybrid multilevel inverter topology with low switching frequency modulation techniques for lower order harmonic elimination
Author | Siddique, Marif Daula |
Author | Bhaskar, Mahajan Sagar |
Author | Rawa, Muhyaddin |
Author | Mekhilef, Saad |
Author | Memon, Mudasir Ahmed |
Author | Padmanaban, Sanjeevikumar |
Author | Almakhles, Dhafer J. |
Author | Subramaniam, Umashankar |
Available date | 2025-03-06T08:50:28Z |
Publication Date | 2020 |
Publication Name | IET Power Electronics |
Resource | Scopus |
Identifier | http://dx.doi.org/10.1049/iet-pel.2020.0620 |
ISSN | 17554535 |
Abstract | A new single-phase asymmetrical multilevel inverter (MLI) is presented in this study. The proposed topology generates a staircase output voltage waveform with a maximum number of levels using less number of components compared to several existing and recent topologies. The basic module consists of a combination of two isolated DC sources with ten switches that produce all the possible number of levels. Other advantages of the proposed MLI include improved output voltage performance and a low blocking voltage of the switches. The low switching frequency pulse width modulation (LSF-PWM) technique has been used for the generation of gate pulses. In the LSF technique, selective harmonic elimination (SHE) and fundamental switching frequency PWM techniques have been discussed for the better output voltage waveform. The optimised switching angles with SHEPWM has been calculated using particle swarm optimisation considering the different combination of the elimination of lower order harmonics. Simulation work was carried out using MATLAB/SIMULINK, and a prototype was implemented to validate the proposed MLI module. Simulation and experimental results have been provided in the study to show the performance of the proposed topology with these modulation techniques. |
Sponsor | This project was funded by the Deanship of Scientific Research (DSR), King Abdulaziz University, Jeddha, Saudi Arabia under the grant no. (KEP-Msc-4-135-39). The authors, therefore, acknowledge with thanks DSR technical and financial support. |
Language | en |
Publisher | John Wiley and Sons Inc |
Subject | Single-Phase Asymmetrical MLI Staircase Output Voltage Low Blocking Voltage LSF-PWM Technique Particle Swarm Optimization |
Type | Article |
Pagination | 4117-4127 |
Issue Number | 17 |
Volume Number | 13 |
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Electrical Engineering [2811 items ]