Hierarchical Floor Plan For Vlsi Integrated Circuits Based On Analytical Techniques

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contributor.author Al Mohannadi, A. L. en_US
date.accessioned 2009-11-25T13:03:32Z en_US
date.available 2009-11-25T13:03:32Z en_US
date.issued 1990 en_US
identifier.citation Engineering Journal of Qatar University, 1990, Vol. 3, Pages 315-331. en_US
identifier.uri http://hdl.handle.net/10576/7840 en_US
description.abstract The physical design of electronic circuits consists of transforming a design specification into a representation to be used in the manufacture of the physical circuits. At Very Large Scale Integration (VLSI) level it becomes diffcult to position or place all circuit elements on the layout surface and to interconnect them together in a one step process. Hierarchical approaches make the placement problem simpler and more easily solved. By partitioning the placement problem into several subproblems, the solution of each subproblem can be obtained and verified in short time. The technique presented supports a design hierarchy whilst maintaining -knpwiedge of global relations between the various components in the floor plan. The paper introduces a new technique where virtual VO pins are placed on the periphery of each hierarchical block to represent the inter-block wiring. The technique allows for variable sized blocks so that the area requirement for any block is allowed to be adjusted during the floor plan optimisation process. It offers all of the benefit of a hierarchical approach whilst maintaining a global view of the wiring and geometrical requirements without the need to smash the hierarchy. A detailed derivation of the technique is given and its performance is demostrated through an example. en_US
language.iso en en_US
publisher Qatar University en_US
subject Electronics en_US
title Hierarchical Floor Plan For Vlsi Integrated Circuits Based On Analytical Techniques en_US
type Article en_US
identifier.pagination 315-331 en_US
identifier.volume 3 en_US


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