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AuthorSiddique, Marif Daula
AuthorMekhilef, Saad
AuthorShah, Noraisyah Mohamed
AuthorSarwar, Adil
AuthorIqbal, Atif
AuthorTayyab? Mohammad
AuthorAnsari, Mohsin Karim
Available date2020-08-18T08:34:46Z
Publication Date2019
Publication NameIEEE Access
ResourceScopus
ISSN21693536
URIhttp://dx.doi.org/10.1109/ACCESS.2019.2925277
URIhttp://hdl.handle.net/10576/15683
AbstractThe inceptions of multilevel inverters (MLI) have caught the attention of researchers for medium and high power applications. However, there has always been a need for a topology with a lower number of device count for higher efficiency and reliability. A new single-phase MLI topology has been proposed in this paper to reduce the number of switches in the circuit and obtain higher voltage level at the output. The basic unit of the proposed topology produces 13 levels at the output with three dc voltage sources and eight switches. Three extentions of the basic unit have been proposed in this paper. A detailed analysis of the proposed topology has been carried out to show the superiority of the proposed converter with respect to the other existing MLI topologies. Power loss analysis has been done using PLECS software, resulting in a maximum efficiency of 98.5%. Nearest level control (NLC) pulse-width modulation technique has been used to produce gate pulses for the switches to achieve better output voltage waveform. The various simulation results have been performed in the PLECS software and a laboratory setup has been used to show the feasibility of the proposed MLI topology. - 2013 IEEE.
SponsorThis publication was made possible by QU High Impact Grant # [QUHI-CENG-19/20-2] from Qatar University. The statements made herein are solely the responsibility of the authors. The publication charges are funded by the Qatar National Library, Doha, Qatar.
Languageen
PublisherInstitute of Electrical and Electronics Engineers Inc.
SubjectDC-AC converter
multilevel inverter
nearest level control (NLC)
reduce switch count
TitleLow Switching Frequency Based Asymmetrical Multilevel Inverter Topology with Reduced Switch Count
TypeArticle
Pagination86374-86383
Volume Number7
dc.accessType Abstract Only


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