Nine-level asymmetrical single phase multilevel inverter topology with low switching frequency and reduce device counts

Abstract

This paper presents a new asymmetrical single-phase multilevel inverter topology capable of producing nine-level output voltage with reduce device counts. In order to obtain the desired output voltage, dc sources are connected in all the combination of addition and subtraction through different switches. Proposed topology results in reduction of dc source, switch counts, losses, cost and size of the inverter. Comparison between the existing topologies shows that the proposed topology yields less component counts. Proposed topology is modeled and simulated using Matlab-Simulink software in order to verify the performance and feasibility of the circuit. A low frequency switching strategy is also proposed in this work. The results show that the proposed topology is capable to produce a nine-level output voltage with less number of component counts and acceptable harmonic distortion content.