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AuthorMorsy, A. S.
AuthorEnjeti, P.
AuthorAhmed, S.
AuthorMassoud, Ahmed
Available date2022-03-23T07:01:05Z
Publication Date2014
Publication NameConference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
ResourceScopus
Identifierhttp://dx.doi.org/10.1109/APEC.2014.6803468
URIhttp://hdl.handle.net/10576/28821
AbstractThis paper introduces a PLL characterized by fast dynamics, wide stability range and minimal deviations. The proposed PLL is based on a frequency adaptive filtering stage to minimize the frequency and phase deviations under unbalanced conditions and harmonic distortions. Furthermore, a simple mathematical formula is introduced to modify the conventional synchronous frame based PLL to provide more stabilization points for the PLL. The advantages of the proposed PLL are verified through simulations.
SponsorPhase locked
Sponsorloop
Sponsorgrid faults
Languageen
PublisherInstitute of Electrical and Electronics Engineers Inc.
SubjectPhase locked
loop
grid faults
TitlePhase locked loop with fast tracking over wide stability range under grid faults
TypeConference Paper
Pagination1263-1267
dc.accessType Abstract Only


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