Phase locked loop with fast tracking over wide stability range under grid faults
Author | Morsy, A. S. |
Author | Enjeti, P. |
Author | Ahmed, S. |
Author | Massoud, Ahmed |
Available date | 2022-03-23T07:01:05Z |
Publication Date | 2014 |
Publication Name | Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC |
Resource | Scopus |
Identifier | http://dx.doi.org/10.1109/APEC.2014.6803468 |
Abstract | This paper introduces a PLL characterized by fast dynamics, wide stability range and minimal deviations. The proposed PLL is based on a frequency adaptive filtering stage to minimize the frequency and phase deviations under unbalanced conditions and harmonic distortions. Furthermore, a simple mathematical formula is introduced to modify the conventional synchronous frame based PLL to provide more stabilization points for the PLL. The advantages of the proposed PLL are verified through simulations. |
Sponsor | Phase locked |
Sponsor | loop |
Sponsor | grid faults |
Language | en |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Subject | Phase locked loop grid faults |
Type | Conference Paper |
Pagination | 1263-1267 |
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Electrical Engineering [2649 items ]