Reduced switch count-based N-level boost inverter topology for higher voltage gain
المؤلف | Siddique, Marif Daula |
المؤلف | Reddy, B. Prathap |
المؤلف | Iqbal, Atif |
المؤلف | Mekhilef, Saad |
تاريخ الإتاحة | 2022-03-31T08:05:50Z |
تاريخ النشر | 2020 |
اسم المنشور | IET Power Electronics |
المصدر | Scopus |
المعرّف | http://dx.doi.org/10.1049/iet-pel.2020.0359 |
الملخص | This study proposes a new boost inverter based on a switched-capacitor concept with reduced switch count. The basic unit is a five-level topology, which inherently generates the AC output voltage with the self-voltage balancing of the capacitors. A conventional carrier-based sinusoidal modulation technique has been designed to maintain the capacitor voltage up to the input source voltage. The N-level structure of the proposed basic unit is also presented, which has the additional advantage of higher voltage gain with a single input. A detailed comparison with other similar topologies has been carried out. A laboratory prototype has been used to test the workability of the proposed basic unit and its extension for seven-level through several results. |
راعي المشروع | This publication was made possible by Qatar University-Marubeni Concept to Prototype Development Research grant # [M-CTP-CENG-2020-2] from the Qatar University. The statements made herein are solely the responsibility of the authors. |
اللغة | en |
الناشر | Institution of Engineering and Technology |
الموضوع | Gain measurement Topology Boost inverters Capacitor voltages Level structure Output voltages Reduced switch Sinusoidal modulation Switched capacitor Voltage balancing Electric inverters |
النوع | Article |
الصفحات | 3505-3509 |
رقم العدد | 15 |
رقم المجلد | 13 |
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