HD number plate localization and character segmentation on the Zynq heterogeneous SoC

Abstract

Automatic number plate recognition (ANPR) systems have become widely used in safety, security, and commercial aspects. A typical ANPR system consists of three main stages: number plate localization (NPL), character segmentation (CS), and optical character recognition (OCR). In recent years, to provide a better recognition rate, high-definition (HD) cameras have started to be used. However, most known techniques for standard definition (SD) are not suitable for real-time HD image processing due to the computationally intensive cost of processing several-folds more of image pixels, particularly in the NPL stage. In this paper, algorithms suitable for hardware implementation for NPL and CS stages of an HD ANPR system are presented. Software implementation of the algorithms was carried on as a proof of concept, followed by hardware implementation on a heterogeneous system-on-chip (SoC) device that contains an ARM processor and a field-programmable gate array (FPGA). Heterogeneous implementation of these stages has shown that this HD NPL algorithm can localize a number plate in 16.17 ms, with a success rate of 98.0%. The CS algorithm can then segment the detected plate in 0.59 ms, with a success rate of 99.05%. Both stages utilize only 21% of the available on-chip configurable logic blocks.